1. Field of the Invention
The present invention relates generally to analog-to-digital converters, and, more particularly, to an analog-to-digital converter architecture using a capacitor array structure.
2. Art Background
Low voltage analog design needs to comply with the ever decreasing digital supply voltage used for an entire mixed-signal chip structure. Supply voltages in deep submicron CMOS technologies decrease constantly due to the short channel effects, and, thus, the need arises for low voltage analog-to-digital converters. A flash analog-to-digital converter (“ADC”), also known as a parallel ADC, is the fastest way to convert an analog signal to a digital signal. Generally, a flash ADC is comprised of multiple cascading high-speed comparator devices, each comparator device having two pair of inputs coupled to a resistive divider circuit and an output coupled to a digital encoder.
In a conventional ADC, each comparator device experiences a different common-mode input voltage, which may prove challenging in the design of the comparator device. In addition, each comparator device requires two pairs of inputs, which may increase the complexity of the comparator device and may create a larger undesired input offset voltage. Thus, what is needed is an architecture containing comparator devices, each comparator device experiencing an identical common-mode input voltage at a desired voltage and having only one pair of inputs.